Design a code converter that converts input code to output code, where the input code (ABCD) is to be in weighted "4, 2, 3, 1" code (see HW1/Q8) and the output (WXYZ) is represented in BCD. All unused input codes and outputs must be taken as "don't care" conditions. Another output called the Valid (V) is also available at the output which is set to logic value "1" if the "input code" is a valid "4, 2, 3, 1" code and it is set to logic value "0" if the input code is an invalid code. List of components available to you for design are given below in two separate "component sets": Set A: 2x 2 - input OR gates, 6x 2 - input AND gates, 4x NOT gates and 2x 2 - input XOR gates. Set B: 5x 8 - to - l MUXs (multiplexers) and many inverters. i) Draw the system truth table. ii) Using K - maps obtain the optimized output functions. iii) If necessary, manipulate output equations to get expressions suitable for implementation with the given component set. Show all algebraic manipulations. iv) Implement using available component set A. v) Implement outputs 2 and V using available component set B