Design a combinational 2-bit greater-than circuit using gate-level logical operators only. Name the design as gt2. The interface of the design and its function are given in the table below. where a[1] and b[1] are the most significant bits of inputs, and a[0] and b[0] are the least significant bits of inpuls. a>b means that the decimal value of a is larger than that of b. In other words, a>b if (1) a(1)>b(1), or (2)a(1)==b(1) and a(0)>b(0) Note that each VHDL entity can be associated with multiple architectures for different models. For this design, create two different architectures as follows. (a) [Dataflow Model] Refer to the code example in Listing 1.2 in Chu's book, create a gate-level architecture for this design. Name this architecture as sop_arch. (b) [Structural Model] Construct a structural architecture for this design. - First you need to build 1-bit comparator that have two outputs gt and eq indicating one input is larger than the other, or both are the same. - Then, build the structural model for the 2-bit greater-than circuit by using the 1-bit component plus other necessary components. Name this architecture as struct_arch. Refer to the code example in Listing 1.3 in Chu's book on an example of a structural model. What to do. - For each model, simulate it by reusing and making necessary changes to the testbench code in Listing 1.6 in Chu's book. - Make sure that the testbench simulates the design with a sufficient and diverse number of input patterns. - Use appropriate concurrent statements to model the above problems. - Implement the design, and generate the bitstream files targeting the Zedboard