Design a cost-effective digital logic circuit for generating a navigation digital real-time map in a smart city metro by controlling a flashing light which starts flashing just .5 miles before the metro approaches a station. Assume the map covers 32 stations across the whole smart city, design the circuit using a minimum number and smallest size of decoders in addition toadditional components.

Q2. Design a cost-effective digital logic circuit for generating a navigation digital real-time map in a smart city metro by controlling a flashing light which starts flashing just .5 miles before the metro approaches a station. Assume the map covers 32 stations across the whole smart city, design the circuit using a minimum number and smallest size of decoders in addition to additional components. The process takes place by using an RFID (Radio Frequency Identification) Reader installed at the train, and RFID batteryless tags installed along the railway. Each tag has memory which stores a unique code in addition to a 5 -bit number corresponding to a particular station. As soon as the train is within .5 miles of a particular station, the associated RFID tag transmits a 5-bit unique encoded number corresponding to the station in its vicinity to the input of the decoder circuit for controlling the flashing light. Only one flashing light should operate at one time. Model the described circuit using Verilog in addition to the test bench and timing diagram using a suitable testing input data corresponding to the unique 5-bit code in a report. The project should be tested in the lab, and the report submitted hard copy. Groups of no more than 5 students are allowed