Question: Design a Mealy FSM based sequence detector ( only state diagram and state table ) that can detect the sequence 1 , 0 , 0

Design a Mealy FSM based sequence detector (only state diagram and state table)
that can detect the sequence 1,0,0,1,1. The sequence detector should allow
overlap. Write a VHDL code in vivado that implements the described sequence detector. Clearly mark the start/reset state and use asynchronous active high reset to reset the sequence detector.

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