Design a memory address decoding system for a microprocessor using AND, OR and NOT gates with the following specification Memory address bus width is 18 bits wide Memory data bus width is 8 bits wide. We require 8K of ROM starting at address 0000016. 48K of data RAM ROM and data RAM address is to be continuous 16 bytes of individual I'O that is memory mapped starting at address 2000016 ROM memory chips available are organized as 4K x 8 bits (4K address, 1 byte data) with one CE (chip enable) RAM memory chips available are organized as 8K x 8 bits with one CE (chip enable) 256 bytes of stack RAM at an address of your choice An additional 16K of data RAM memory may be added at a later date Draw your memory map and a simple circuit diagram showing your address decoding circuit for the memory CE (chip enable) and I/O CE. Show intermediate working Design a memory address decoding system for a microprocessor using AND, OR and NOT gates with the following specification Memory address bus width is 18 bits wide Memory data bus width is 8 bits wide. We require 8K of ROM starting at address 0000016. 48K of data RAM ROM and data RAM address is to be continuous 16 bytes of individual I'O that is memory mapped starting at address 2000016 ROM memory chips available are organized as 4K x 8 bits (4K address, 1 byte data) with one CE (chip enable) RAM memory chips available are organized as 8K x 8 bits with one CE (chip enable) 256 bytes of stack RAM at an address of your choice An additional 16K of data RAM memory may be added at a later date Draw your memory map and a simple circuit diagram showing your address decoding circuit for the memory CE (chip enable) and I/O CE. Show intermediate working