The unit cell of a memory device has aspect ratio $($height divided by width$)$ of $1\mathrm{.}5$ as

shown in the following figure. Using this shape of unit cell we are going to design $64$

Mega Byte memory chip. How many rows and how many columns are you going to

assign for minimum die size? This memory is accessed using $16-$bit wide of data bus.

Assume that thickness of decoder is exponentially increasing with the number of

address bits. So$,$ the width of row decoder is $**e^R$ where $2^R$ is total number of rows.

The same is true for column decoder. The height of column decoder is $**e^C$ where $2^C$

is total number of columns divided by bus width $(16$ bits$).$