Design a non-pipeline datapath for a single-cycle MIPs processor in Verilog. Datapath from below chart

It will have following inputs and outputs

Module Name: mips_simple_datapath
Port Name	Direction	Width	Function
clk	Input	1	Global clock
instruction	Input	32	Instruction data from Instruction Memory
PCSrc	Input	1	Source of the PC
ALUSrc	Input	1	Source of the 2nd operand of the ALU
RegWrite	Input	1	Write data in the register file
RegDst	Input	1	Indicates the register destination for the Write register
MemtoReg	Input	1	Register File input multiplixer
ALUCtrl	Input	4	Indicates which operation that the ALU should perform
PC	Output	32	Program Counter
Zero	Output	1	ALU zero indicator
dAddress	Output	32	Address for data Memory
dWriteData	Output	32	Data to write into data memory
dReadData	Input	32	Data read from data memory

It needs to pass the following testbench

`timescale 1ns / 100ps module tb_simple_datapath(); reg clk; //reg [8:0] tb_ControlSignals; reg tb_PCSrc, tb_ALUSrc, tb_RegWrite, tb_RegDst, tb_MemtoReg, tb_MemWrite; reg [3:0] tb_ALUCtrl; wire [31:0] tb_PC, tb_dReadData, tb_dWriteData, tb_dAddress; reg [31:0] tb_instruction; wire tb_Zero; integer i, errors; // Tasks task set_control_signals; input PCSrc, ALUSrc, RegWrite, RegDst, MemtoReg, MemWrite; input [3:0] ALUCtrl; begin tb_PCSrc = PCSrc; tb_ALUSrc = ALUSrc; tb_RegWrite = RegWrite; tb_RegDst = RegDst; tb_MemtoReg = MemtoReg; tb_MemWrite = MemWrite; tb_ALUCtrl = ALUCtrl; end endtask /* Instruction Phase: * 0: Positive Clock Edge * 2: Propagation delay: setup signals for next clock * 5: Negative edge * 7: Check data going into clock cycle * 10: Positive Edge * * This task will go from "2" to "7" (assume at step 2) */ task execute_instruction; input PCSrc, ALUSrc, RegWrite, RegDst, MemtoReg, MemWrite; input [3:0] ALUCtrl; input [31:0] instruction; begin set_control_signals(.PCSrc(PCSrc), .ALUSrc(ALUSrc), .RegWrite(RegWrite), .RegDst(RegDst), .MemtoReg(MemtoReg), .ALUCtrl(ALUCtrl), .MemWrite(MemWrite)); tb_instruction = instruction; #3 clk = 0; // assume clock is high for #2: change to negative edge #3 later (at #5) #2 clk = 0; // stay low another #2 end endtask task execute_rtype_alu_instruction; input [3:0] ALUCtrl; input [31:0] instruction; begin execute_instruction(.PCSrc(0), .ALUSrc(0), .RegWrite(1), .RegDst(1), .MemtoReg(0), .ALUCtrl(ALUCtrl), .MemWrite(0), .instruction(instruction)); end endtask task execute_sw_instruction; input [31:0] instruction; execute_instruction(.PCSrc(0), .ALUSrc(1), .RegWrite(0), .RegDst(0), .MemtoReg(0), .ALUCtrl(4'b0010) /* add */, .MemWrite(1), .instruction(instruction)); endtask task execute_lw_instruction; input [31:0] instruction; // Control: .PCSrc(0), .ALUSrc(1), .RegWrite(1), .RegDst(0), .MemtoReg(1), .ALUCtrl(), .MemWrite(0)); execute_instruction(.PCSrc(0), .ALUSrc(1), .RegWrite(1), .RegDst(0), .MemtoReg(1), .ALUCtrl(4'b0010) /* add */, .MemWrite(0), .instruction(instruction)); endtask task execute_beq_instruction; input taken; input [31:0] instruction; execute_instruction(.PCSrc(taken/*tb_Zero*/), .ALUSrc(0), .RegWrite(0), .RegDst(0), .MemtoReg(0), .ALUCtrl(4'b0110) /* subtract */, .MemWrite(0), .instruction(instruction)); endtask /* Instruction Phase: * 0: Positive Clock Edge * 2: Propagation delay: setup signals for next clock * 5: Negative edge * 7: Check data going into clock cycle * 10: Positive Edge * * This task will go from "7" to "2" (assume at step 2) */ task check_initial_pc; input [31:0] expected_new_pc; begin if (expected_new_pc != tb_PC) begin $display("*** Error: PC=%h but expect %h at time %0t", tb_PC, expected_new_pc, $time); errors = errors + 1; end else $display("Correct PC=%h at time %0t", tb_PC, $time); #3 clk = 1; // assume clock is low for #2: Change to positive edge #2 later #2 clk = 1; // stay high another #2 end endtask task check_alu; input [31:0] expected_alu; input [31:0] expected_new_pc; begin if (expected_alu != tb_dAddress) begin $display("*** Error: ALU Result=%h but expect %h at time %0t", tb_dAddress, expected_alu, $time); errors = errors + 1; end else begin $display("Correct ALU Result=%h at time %0t", tb_dAddress, $time); if (tb_dAddress == 0 && tb_Zero !=1) begin $display("*** Error: ALU Result=0 but Zero!=1 at time %0t", $time); errors = errors + 1; end if (tb_dAddress != 0 && tb_Zero ==1) begin $display("*** Error: ALU Result!=0 but Zero=1 at time %0t", $time); errors = errors + 1; end end check_initial_pc(expected_new_pc); end endtask // Check the write address and the write value task check_sw; input [31:0] expected_write_address; input [31:0] expected_write_data; input [31:0] expected_new_pc; begin if (expected_write_address != tb_dAddress) begin $display("*** Error: Write address=%h but expect %h at time %0t", tb_dAddress, expected_write_address, $time); errors = errors + 1; end else $display("Correct: Write address=%h at time %0t", tb_dAddress, $time); if (expected_write_data != tb_dWriteData) begin $display("*** Error: Write data=%h but expect %h at time %0t", tb_dWriteData, expected_write_data, $time); errors = errors + 1; end else $display("Correct: Write data=%h at time %0t", tb_dWriteData, $time); check_initial_pc(expected_new_pc); end endtask // Check the write address and the write value task check_lw; input [31:0] expected_read_address; input [31:0] expected_read_data; input [31:0] expected_initial_pc; begin if (expected_read_address != tb_dAddress) begin $display("*** Error: Read address=%h but expect %h at time %0t", tb_dAddress, expected_read_address, $time); errors = errors + 1; end else $display("Correct: Read address=%h at time %0t", tb_dAddress, $time); if (expected_read_data != tb_dReadData) begin $display("*** Error: Read data=%h but expect %h at time %0t", tb_dReadData, expected_read_data, $time); errors = errors + 1; end else $display("Correct: Read data=%h at time %0t", tb_dReadData, $time); check_initial_pc(expected_initial_pc); end endtask // Check the write address and the write value task check_zero; input expected_zero; input [31:0] expected_initial_pc; begin if (expected_zero != tb_Zero) begin $display("*** Error: Zero=%b but expect %b at time %0t", tb_Zero, expected_zero, $time); errors = errors + 1; end else $display("Correct: Zero=%b at time %0t", tb_Zero, $time); check_initial_pc(expected_initial_pc); end endtask function [31:0] build_r_inst; //input [5:0] op; input [4:0] rs, rt, rd, shamt; input [5:0] funct; begin // rs: first operand, rt: second operand, rd: destination //build_r_inst = {op, rs, rt, rd, shamt, funct}; // OP always zero for r type instructions build_r_inst = {5'b00000, rs, rt, rd, shamt, funct}; end endfunction function [31:0] build_i_inst; input [5:0] op; input [4:0] rs, rt; input [15:0] constant; begin build_i_inst = {op, rs, rt, constant}; end endfunction // Datapath module mips_simple_datapath datapath(.clk(clk), .PCSrc(tb_PCSrc), .ALUSrc(tb_ALUSrc), .RegWrite(tb_RegWrite), .RegDst(tb_RegDst), .MemtoReg(tb_MemtoReg), .ALUCtrl(tb_ALUCtrl), .instruction(tb_instruction), .PC(tb_PC), .Zero(tb_Zero), .dReadData(tb_dReadData), .dWriteData(tb_dWriteData), .dAddress(tb_dAddress)); // Data Memory localparam DATA_MEMORY_DEPTH = 64; reg [31:0] data_memory[DATA_MEMORY_DEPTH-1:0]; initial for(i=0;i>2] >2]; initial begin errors = 0; //shall print %t with scaled in ns (-9), with 2 precision digits, and would print the " ns" string $timeformat(-9, 0, " ns", 20); $display("*** Start of Simulation ***"); // Initialize the inputs clk = 0; set_control_signals(.PCSrc(0), .ALUSrc(0), .RegWrite(0), .RegDst(0), .MemtoReg(0), .ALUCtrl(0), .MemWrite(0)); tb_instruction = 0; #5 // Load memory locations 1*4 to 31*4 into registers $1 to $31 (skip 0 since you shouldn't be able to write to it) // The memory locations are preloaded with 0,1,...,31 $display("*** Checking memory loading with 'lw' instruction"); for (i=1;i