Design a state$-$machine to give an output $\text{'}1\text{'}$ when the number of $A\text{'}$s are even and number of B$\text{'}$s are odd. The input is in the form of a serial$-$stream $($one$-$bit per clock cycle$).$ The input $s$ could be of the type A$,$ B $.$ At any given clock cycle, the output is a $\text{'}1\text{'},$ provided the number of $A^{\text{'}}\text{'}$s are even and number of B$\text{'}$s are odd. At any given clock cycle, the out put is a $\text{'}0\text{'},$ if the above condition is not satisfied.