Design a synchronous sequential circuit that takes a one$-$bit stream x$0$x$1$x$2...$ as input, and outputs a one$-$bit stream y$0$y$1$y$2....$ The i$-$th output bit yi is $1$ if and only if the four most recently read input bits xi$3$xi$2$xi$1$xi have odd parity. Here is an example. At the beginning of the input, four bits are not read. Assume that the missing bits are $0($that is$,$ x$3=$ x$2=$ x$1=0).$

Input: $0100110100111010...$

Output: $0111000101001110...$