Design a two$-$stage CMOS operational amplifier with the following specifications:

$*$ Open$-$loop voltage gain $($Av$)$: $>=80$ dB

$*$ Unity$-$gain bandwidth: $>=10$ MHz

$*$ Phase margin: $>=60$

$*$ Power consumption: $<=2$ mW at VDD $=3\mathrm{.}3$ V

$*$ Output swing: $\backslash$pm $1\mathrm{.}5$ V

$*$ Load capacitance: $10$ pF