Question: Design an FSM-based 3-bit binary counter using Verilog HDL which is able to count-up from 3'do to 3'd7 and repeats. Assume that the binary counter

Design an FSM-based 3-bit binary counter using Verilog HDL which is

Design an FSM-based 3-bit binary counter using Verilog HDL which is able to count-up from 3'do to 3'd7 and repeats. Assume that the binary counter counts at every positive edge CLK with asynchronous RESET and the start counting sequence is 000. Design, simulate and verify the design from the generated simulation waveform

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