Question: Design (and draw a schematic for) an asynchronously resettable D latch and asynchronously resettable D flip-flop using logic gates (e.g. NOT, AND, NOR, NAND).

  1. Design (and draw a schematic for) an asynchronously resettable D latch and asynchronously resettable D flip-flop using logic gates (e.g. NOT, AND, NOR, NAND).

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