Design and implement a $8-$bit resetable up count, that stops counting when max is reached. The ports are:

module counter$($ output u$8\_$t count, input u$8\_$t max,

input logic clk$,$ reset$)$;

The u$8\_$t type is defined in the test bench. count is the counter's output. The counter should increment by one for even positive edge clock until the max is reached. The counter should not increment when max is reached. The counter is reset if reset $=1$ when a positive edge clock occurs.

The $8-$bit comparator module, cmp$,$ must be used to check when max is reached. The test bench will set max to $150$ for its testing.

$//$ include cmp module

module cmp$($output logic yes, input u$8\_$t a$,$ b $)$;

logic $[7$:$0]$ temp;

assign temp$[0]=$ ~$(|$a$[0]^$ b$[0])$;

assign temp$[1]=$ ~$(|$a$[1]^$ b$[1])$;

assign temp$[2]=$ ~$(|$a$[2]^$ b$[2])$;

assign temp$[3]=$ ~$(|$a$[3]^$ b$[3])$;

assign temp$[4]=$ ~$(|$a$[4]^$ b$[4])$;

assign temp$[5]=$ ~$(|$a$[5]^$ b$[5])$;

assign temp$[6]=$ ~$(|$a$[6]^$ b$[6])$;

assign temp$[7]=$ ~$(|$a$[7]^$ b$[7])$;

assign yes $=$ temp$[0]$ & temp$[1]$ & temp$[2]$ & temp$[3]$ & temp$[4]$ & temp$[5]$ & temp$[6]$ & temp$[7]$;

endmodule

module counter$($ output u$8\_$t count, input u$8\_$t max,

input logic clk$,$ reset$)$;

logic m$\_$test;

assign m$\_$test$=1\text{'}$b$0$;

cmp test $($

$.$yes$($m$\_$test$),$

$.$a$($count$),$

$.$b$($max$)$

$)$;

$//$ complete the rest

always$\_$ff @$($posedge clk or posedge reset$)$ begin

if $($reset$)$ begin

count $<=8\text{'}$b$00000000$;

end else begin

m$\_$test $<=$ ~m$\_$test;

if $($test$.$yes && $($count $<$ max$)$ && $($count $\%2==0))$ begin

count $<=$ count $+8\text{'}$b$00000001$;

end

end

end

endmodule

typedef logic $[7$:$0]$ u$8\_$t;

module main;

u$8\_$t count;

logic clk$,$ reset;

logic pass$\_$fail;

u$8\_$t expected, max;

integer cycles;

task clock$\_$cycle$($integer n$)$;

repeat$($ n $)$ begin

clk $=0$; #$5$;

clk $=1$; #$5$;

end

endtask

counter dut$($ count, max, clk$,$ reset $)$;

initial begin

max $=150$;

expected $=0$;

cycles $=0$;

pass$\_$fail $=1$;

clk $=0$;

reset $=1$; clock$\_$cycle$(1)$; reset $=0$;

for$($ cycles $=0$; cycles $<$ max$+1$; cycles $=$ cycles $+1)$ begin

if $($ count $!==$ expected $)$ begin

$display$($ "failed: count$=\%1$d expected$=\%1$d$",$ count,expected$)$;

pass$\_$fail $=0$;

end

expected $=$ expected $+1$;

clock$\_$cycle$(1)$;

end

clock$\_$cycle$(2)$;

if $($ count $!==$ max $)$ begin

$display$($ "failed: count$=\%1$d max$=\%1$d$",$ count,max$)$;

pass$\_$fail $=0$;

end

if $($ pass$\_$fail $==1)$ $display$("$

Test passed"$)$;

else $display$("$

Test failed"$)$;

end

endmodule

RTL Control of mini$-$ALU

Error Output $--------------$

module.v:$23$: error: Unresolved net$/$uwire m$\_$test cannot have multiple drivers.

module.v:$23$: error: Output port expression must support continuous assignment.

module.v:$23$: : Port $1($yes$)$ of cmp is connected to m$\_$test

module.v:$34$: error: m$\_$test Unable to assign to unresolved wires.

$3$ error$($s$)$ during elaboration.

solve the error so that it can provide the expected output