Design and implement a state machine $($using JK flip$-$flops$)$ that functions as a $3-$bit sequence

generator that produces the following binary patterns.

$($ULO $1,2,3,4,5,8)[15$ Marks$]$

$\frac{001}{1},\frac{011}{0},\frac{010}{1},\frac{111}{0},\frac{101}{1},\frac{100}{0}$

$[repeat]\frac{001}{1},\frac{011}{0},\frac{010}{1},\frac{111}{0},\frac{101}{1},\frac{100}{0}$

$[repeat]\frac{001}{1},\frac{011}{0},\frac{010}{1},\frac{111}{0},\frac{101}{1},\frac{100}{0}$

Everytime the sequence reach $001,010$ and $101,$ the output $F$ must be $1.$

JK FF State Table

A$.$ Design the STD$.$ Explain why your design is safe.

B$.$ Implement the State Transition Table with FF input

C$.$ Derive the FF inputs from K$-$Maps

D$.$ Sketch the final circuit design

E$.$ Reimplement your design using VHDL instead.

$($ULO $3,4)[2\mathrm{.}5+2\mathrm{.}5$ Marks$]$

$($ULO $2)[2\mathrm{.}5$ Marks$]$

$($ULO $1,2)[1+1\mathrm{.}5$ Marks$]$

$($ULO $8)[2\mathrm{.}5$ Marks$]$

$($ULO $5)[2\mathrm{.}5$ Marks$]$

No need for a full VHDL implementation, just the Architecture and combinational process

is enough. You may rename your states eg$.$ One, Three, Two, etc.