Question: Design and implement in Verilog (gate level modeling) a 4-bit ALU according to the following specifications: Build the 1-bit ALU for bits 0 to 2

Design and implement in Verilog (gate level modeling) a 4-bit ALU

Design and implement in Verilog (gate level modeling) a 4-bit ALU according to the following specifications: Build the 1-bit ALU for bits 0 to 2 (without the SET line but including the LESS input) Your 1-bit ALU is to do ADDITION, SUBTRACTION, AND and OR. Use good hierarchical design (through modules in Verilog)

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