Objective: Develop Verilog code using top down design Lab Goal: For this lab, you will write the Verilog code for a 4-bit arithmetic/logic unit (ALU) according to the specifications outlined under the specifications section of this document. You will write a Test Bench to thoroughly test your design and you will program the DEO-CV board to implement your design. Specifications: The ALU operate on inputs that are 4 bits wide. It will take as input aluin_a and aluin_b, a carry in named Cin and operation code named OPCODE. Inputs aluin_a, aluin_b and OPCODE are 4 bits wide. Cin is 1-bit wide. The output will be alu out and Cout. Output alu out (which is the result of the ALU operation) is 4 bits wide. Cout is the carry out and will be 1 bit. A 1-bit flag will be set on overflow (named OF), assume this is the overflow for numbers which have sign. A test bench should be created to thoroughly test the ALU. Objective: Develop Verilog code using top down design Lab Goal: For this lab, you will write the Verilog code for a 4-bit arithmetic/logic unit (ALU) according to the specifications outlined under the specifications section of this document. You will write a Test Bench to thoroughly test your design and you will program the DEO-CV board to implement your design. Specifications: The ALU operate on inputs that are 4 bits wide. It will take as input aluin_a and aluin_b, a carry in named Cin and operation code named OPCODE. Inputs aluin_a, aluin_b and OPCODE are 4 bits wide. Cin is 1-bit wide. The output will be alu out and Cout. Output alu out (which is the result of the ALU operation) is 4 bits wide. Cout is the carry out and will be 1 bit. A 1-bit flag will be set on overflow (named OF), assume this is the overflow for numbers which have sign. A test bench should be created to thoroughly test the ALU