Design, enter and simulate a circuit, using Verilog as the primary entry method, that imple$-$

ments the following two output logic functions:

You are to design two functions, $f_1$ and $f_2,$ with four inputs named $x_1,x_0,y_1,$ and $y_0.$ Consider

$x=x_1{x}_0$ to be a number. The four possible patterns of $x_1{x}_0,$ namely $00,01,10,$ and $11$ rep$-$

resent the four numbers $0,1,2,$ and $3,$ respectively. Similarly, consider $Y=y_1{y}_0$ to be another

number with the same four possible values. The function $f_1$ should be $1$ when the number

represented by $x$ is less than or equal to the number represented by $Y($i$.$e$.xY),$ otherwise

$f_1$ should be $0.$ The function $f_2$ should be $1$ when the two numbers represented by X and Y are

equal $($i$.$e$.x=Y),$ otherwise $f_2$ should be $0.$