Design of Finite State Machine (FSM) using Hardware Description Language (HDL)

1 Design of an up-down Red ID counter

In this lab, we will design an up-down Red ID counter using Hardware Description Language (HDL) based on Verilog. A tutorial on using Xilinx ISE tool based on Verilog for sequential circuit design can be found in the Appendix under the section “Lab project assignments” in Blackboard.

Design an up-down Red ID counter using your own Red ID number. In this device, there are two expected inputs, namely U and D (U denotes upward counting and D denotes downward counting), and the outputs of this device are used to represent the actual counted number.

For example, if your Red ID number is “87654321” and your actual input is U, then the outputs of the counter should show the following sequence: 8,7,6,5,4,3,2,1,8 (repeating); If your Red ID number is “87654321” and your actual input is D, then the outputs of the counter should show the following sequence: 8,1,2,3,4,5,6,7,8 (repeating). Note that you need to use binary numbers in the outputs to represent your counted number. For example, if your actual counted number is 8, then you can use “1000” in the outputs to represent that number. You need to design an FSM with appropriate number of states to reflect your counted sequence.

Use Xilinx tool to design a test bench that generates the whole sequence of upward counting as well as downward counting. Show the obtained simulated timing diagram.