Design Problem

Design a Moore FSM that recognizes an input sequence, when interpreted as an unsigned binary number, is a non$-$zero multiple of $4$ but not a multiple of $8.$ While drawing Next State Logic and Output Logic circuits in the Moore FSM Schematic, use three basic gates only $(2-$input AND gates, $2-$input OR gates, NOT gates$).$

Grading Criteria:

$-$State Transition Diagram

$-$Descriptions of States

$-$State Reduction $($if possible$)$

$-$State Transition Table

$-$Output Table

$-$State Encoding

$-$State Transition Table with State Codes

$-$Output Table with State Codes

$-$K$-$Maps

$-$Simplified Expressions of Next State Bits & Output

Moore FSM Circuit Schematic

$-$Next State Logic Circuit

$-$Output Logic

$-$Rest of Schematic