Design Specifications:

Design a Serial Arithmetic Logic Unit $($ALU$)$ that performs a set of operations on up to two $4-$bit binary numbers based on

a $4-$bit operation code $($OpCode$).$

Inputs:

clk: clock input

DATA$[3.\mathrm{.}0]$: $4-$bits of Data $($shared bus between both registers$)$

RESET: Active low reset that sets the ALU to an initial state, with all data set to zero.

OpCode$[5.\mathrm{.}0]$: $6-$bit Control input that represents a code for each operation.

START: $1-$bit Control input that starts the operation after the OpCode has been set.