Design the gate A(B+C) in dynamic logic.

a) Design the schematic.

b) Determine the size of the equivalent transistor of Pull Up Network if each one of the transistors are size (W/L)_n = 3/1 and (W/L)_p = 5/1.

c) Determine the size of the equivalent transistor of Pull Down Network if each one of the transistors are size (W/L)_n = 3/1 and (W/L)_p = 5/1.

d) If the technology used in part b, is Tec = 0.3um and we use minimum L for all transistors. Determine the size of the manufacturable equivalent transistor for the Pull Up Network.

e) If the technology used in part c, is Tec = 0.3um and we use the L necessary for W to be smallest manufacturable size. Determine the size of the manufacturable equivalent transistor for the Pull Down Network.

f) List each NMOS transistor and indicate which ones do not suffer from body effect.