Design using a combinational VHDL process a sign magnitude to twos complement converter using the given algorithm and hardware description. Use the following VHDL entity specifica- tion:

library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all; 

entity converter is port( sign_mag : in std_logic_vector(3 downto 0) ; 

 twos_comp : out std_logic_vector(3 downto 0) ); 

end;

sign magnitude input "001" 3 sel two's complement output sign magnitude input "001" 3 sel two's complement output