Digital Design I HW #$3$

$4\mathrm{.}9)$ An ABCD$-$to$-$seven$-$segment decoder is a combinational circuit that converts a decimal digit in $BCD$ to an appropriate code for the selection of segments in an indicator used to display the decimal digit in a familiar form. The seven outputs of the decoder $($a$,$ b$,$ c$,$ d$,$ e$,$ f$,$ g$)$ select the corresponding segments in the display, as shown in Fig. P$4\mathrm{.}9($a$).$ The numeric display chosen to represent the decimal digit is shown in Fig. P$4\mathrm{.}9($b$).$ Using a truth table and Karnaugh maps, design the BCD$-$to$-$seven$-$segment decoder using a minimum number of gates. The six invalid combinations should result in a blank display.

$($a$)$ Segment designation

$($b$)$ Numerical designation for display

FIGURE P$4.9$

$4\mathrm{.}10)$ Design a four$-$bit combinational circuit $2\text{'}$s complementer. $($The output generates the $2\text{'}$s complement of the input binary number.$)$ Show that the circuit can be constructed with exclusive$-$OR gates. Can you predict what the output functions are for a five$-$bit $2\text{'}$s complementer?

$4\mathrm{.}27)$ A combinational circuit is specified by the following three Boolean functions:

$F_1(A,B,C)={\displaystyle \underset{?}{\overset{?}{}}}(2,4,7)$

$F_2(A,B,C)={\displaystyle \underset{?}{\overset{?}{}}}(0,3)$

$F_3(A,B,C)={\displaystyle \underset{?}{\overset{?}{}}}(0,2,3,4,7)$

Implement the circuit with a decoder constructed with NAND gates and NAND or AND gates connected to the decoder outputs. Use a block diagram for the decoder. Minimize the number of inputs in the external gates.

$4\mathrm{.}34$ b$)$ An $81$ multiplexer has inputs $A,B$ and $C$ connected to the selection inputs $S_2,S_1$ and $S_0,$ respectively. The data inputs $I_0$ through $I_7$ are as follows: $I_1=I_2=0$;$I_3=I_7=1$;$I_4=I_5=D$; and $I_0=I_6=D^{\text{'}}.$ Determine the Boolean function that the multiplexer implements.