Draw a '4-bit asynchronous' and 'synchronous up counter' timing diagram, ( Quartus simulate) to compare the differences.

V cc A VCC B VCC V cc D Q Q Q Q J CK K J ) K J K J K Q QH QH Q [ 10-3] 4 2 (Logic 1) & & FFA FFB FFC FFD Out J QA J QB B J QC J Qp CLK QA CLK Q CLK Qc CLK QD QA K QB K Qc K Qp 1 O