Draw a timing diagram which illustrate the difference between the following VHDL statements Signal a, b,...

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Draw a timing diagram which illustrate the difference between the following VHDL statements Signal a, b, c, d: bit; B<= a after 5 ns; C<= transport a after 5 ns; D <= reject 3ns inertial a after 5 ns; a 1ns 4ns 6ns Draw a timing diagram which illustrate the difference between the following VHDL statements Signal a, b, c, d: bit; B<= a after 5 ns; C<= transport a after 5 ns; D <= reject 3ns inertial a after 5 ns; a 1ns 4ns 6ns

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