Draw the circuit representation of the VHDL code below using D-type flip-flops.

LIBRARY ieee; USE ieee.std-logic1 16 4.all; ENTITY xyz IS PORTclock IN STD_LOGIC STD_LOGIC : BUFFERSTD_LOGIC_VECTOR (3 DOWNTO O))i END xyzi ARCHITECTuRE a oF xyz IS BEGIN PROCESS WAIT UNTIL Clock' EVENT AND Clock = '0'; 0(2) 9(3) END PROCESS; 0(3); w;