3) Draw the circuit representation of the VHDL code below using D-type flip- flops. (15 marks) LIBRARY ieee; USE ieee.std logic 1164.all; ENTITY xyz IS PORT Clock: IN STD LOGIC STD LOGIC STD LOGIC STD LOGIC VECTOR (3 DOWNTO 0) STD LOGIC VECTOR (3 DOWNTO 0) STD LOGIC VECTOR (3 DOWNTO 0) ) Rn DO D1 : OUT END xyz; ARCHITECTURE a OF xyz IS BEGIN PROCESS BEGIN if Rn '0' then