) Draw the initially reset output waveforms for the Flip Flop circuit shown below: DO-0 D1-1 D2-1 D3-1 D1-HD -Q1 Parallel data - inputs p2 data pCLK D3 CLK Q1 02 03 2. B) a) Simplify the following Boolean expression, b) connect the PAL array to construct the logic and c) write VHDL and VERILOG programs to implement the digital circuit. X (AB+ AB) (CD + CD) VERILOC: module Boolean ( output VHDL: entity Boolean is port ( : in bit:out bit): input end entity Boolean; architecture dataflow of Boolean is wire begin assign end architecture dataflow endmodule