2 A) Draw the initially reset output waveforms for the Fip Flop circuit shown below: D1- 1 D2 1 D3 1 Parallel data - Paralld CLR LJ D3 CLK Q1 02 Q3 D Q-Q3 2. B) a) Simplify the following Boolean expression, b) connect the PAL array to construct the logic and c) write VHDL and VERILOG programs to implement the digital circuit. X = ( AB + AB) (CD CD) VERILOG VHDL: module Boolean ( entity Boolean is output input : in bit; : out bit); port ( end entity Boolean; architecture dataflow of Boolean is wire begin assign end architecture dataflow; endmodule