Dynamic scheduling. Consider a dynamically scheduled processor using Tomasulo's algorithm as

demonstrated in class. The Load$/$Store$,$ Floating Point Adder, and Floating$-$Point Multiplier all execute

one instruction at a time There is one functional unit of each type with the specified latency in clock

cycles given below: $(14$ points$)$

Number of Cycles Required by Each Unit

Load$/$Store Unit: $4$

Floating Point Adder: $3$

Floating Point Multiplier: $6$

Integer Adder: I

Branch Operations: $2$

Instructions begin execution $($if possible$)$ on the clock cycle after issue: Note that a fullinstruction gueue

can be issued in the same cycle. The filled in portion below is given as an example of how to complete

the table Read carefully.

Write back occurs at the cycle after the completion of the load or function, that is$,$ if execution begins

at $2$ and takes $4$ cycles $(2,3,4,5)$ then write back begins at $5.$

Fill in the table below to show how each instruction progresses through the corresponding functional unit.

Only complete the table once. START AT CLOCK CYCLE $1.$ As shown

Code

Loop: LOAD.D F$2,$ O$($RI$)$

LOAD.D F$6,0($R$2)$

MULD F$4,$ F$2,$ FO

ADD.D F$6,$ F$4,$ F$6$

STORE.D F$6,0($R$2)$

pADDUI RI$,$R$1,$#$-8$

ADDUI R$2,$R$2,$ #$-8$

GT RI$,$R$5,$ Loop

Functional

Unit

Load buffer

Load buffer

Issue

Execute

Cycles

$2,3,4,5$

$6,7,8,9$

Write

Back

$5$

$9$

Please use these start values.