exam please help!!!

Complete the behavioral VHDL code of a 4-bit down-counter that counts from 14 to 0. The counter has an asynchronous Resetn input that resets the counter back to 14 when Reset = 0 The counter will countdown if and only if it has a nsing edge on its clock and its enable input E is equal to 1. LIBRARY ieee USE ieee std_logic_1164. all USE ENTITY downcount IS PORT (Clack, Resetn. E IN Q:OUT END downcount: ARCHITECTURE Behavior OF downcount IS SIGNAL Count: BEGIN BEGIN IF Resein = '0' THEN EL SIF (Clock'EVENT AND Clock = '1') THEN IF FL THEN ELSE Count Count : END IF O