exam please help!!

Complete the behavioral VHDL code of an Arithmetic Logic Unit that has 4 inputs A B, f and EN. A and B are 16 bits each, fis 3 bits and EN is 1 bit. The ALU has one output that has a size of 16 bits. The below table shows the behavior of the Logic Unit. Note that any change on any input will affect the output ENT S 0 x s will keep its value 1 000 S=A+B S=A-B 1 001 1 010 SEA 1 011 SEB 1 100 s is cleared 1 101 s will have its maximum value 1 110 All the bits of s are set to 1 1 Most significant byte of s equals most significant Byte of B 1 111 Least significant byte of s equals least significant Byte of A LIBRARY ieee : USE USE ENTITY alu IS PORT EN: : S: END alu: ARCHITECTURE Behavior OF alu IS BEGIN BEGIN If THEN CASE IS S ' > WHEN "010" => WHEN "011' => WHEN "100" => Sc= WHEN "110' => S