Example 1. Implementation of a Synchronous Up - Counter Worked by: Instructor of ECET:46 F. F2 Input Logical "1" 1 Ta-FF Tb-FF Tc-FF Td-FF Qa Qb Qc Qd Clock Signal I Enable Asynchronous Reset O Four T - Flip Flops are used to create a 4-bit counter Clock signal is used to synchronize all flip-flops with each other This counter counts from the binary sequence 0000 up to 1111 Table 1: State Table of Synchronous Up - Counter Qd Clock Pulse 1 2 Present State Qd Q Qb 0 0 0 0 0 0 0 1 Qa 0 1 Next State Q Qb 0 0 1 Qa 1 0 0 0 3 0 0 1 1 4 0 1 1 0 1 0 0 0|0||0|0 1 0 0 1 5 6 7 1 0 1 1 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 8 0 1 1 1 0 0 0 0 9 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 1 0 1 1 1 1 0 0 10 11 12 13 14 15 1 1 0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 16 1 1 1 1 0 0 0 0 Answer the following questions for the sequential circuit given in Example 1 for the Synchronous Up - Counter circuit. a. Explain the output of the circuit if two extra T flip-flops are added? b. How many T flip-flops should the circuit have if we want to count from the decimal number 0 up to the decimal number 31? Explain your