Exercise 2: (20 pts) A system has a virtual page number of 24 bits, a physical page number of 12 bits, and a page size of 4 KB. A TLB is used by our system. The page numbers and offset are given in hexadecimal. For each of the following virtual addresses, indicate whether a hit occurs, and if it does, give the physical address: a. Virtual address: 3EF2B476D TLB hit or miss? b. Virtual address: 87ECA4CF3 TLB hit or miss? Physical address: Physical address: Physical address: C. Virtual address: 6E4A39D6A TLB hit or miss? Valid bit Dirty bit Virtual page nbr. Physical page frame nbr. 0 1 9F4325 ESA 1 0 87ECA4 E03 0 0 6E4A39 2F8 1 0 3D7125 FA2 1. What is the role of using cache in memory hierarchy? 2. i) If a direct mapped cache has a hit rate of 95%, a hit time of 4 ns, and a miss penalty of 100 ns, what is the AMAT? ii) If an L2 cache is added with a hit time of 20 ns and a bit rate of 50%, what is the new AMAT