Exercise 3. (15 Marks] Consider a 16-bit computer with a single 4-way cache with 2 sets, a capacity of 32 bytes, and a LRU replacement policy. Consider also the following sequence of memory word addresses. 12, 14, 15, 11, 8, 6, 3, 2, 5, 7, 9, 12, 34, 33, 37, 15 (a) Determine, in binary, the tag, set index, and block offset for each address in the above sequence. Include the byte offset as part of the block offset. Assume the cache is initially empty. During the sequence of address accesses above, determine if each reference results in a cache hit or a cache miss. If the reference results in a cache miss, determine which type of cache miss occurs: cold, conflict, or capacity. You may fill in the below table in order to answer this question. Tag Index Block Offset Hit or Miss Type of Miss Address 12 14 15 11 8 6 3 2 5 7 9 12 34 33 37 15 (b) Create a table which resembles this cache's configuration. Fill that table such that it corresponds to the cache's contents after all addresses in the above sequence have been referenced. (See 3350-L4-CacheExample.pdf")