EXERCISES

Which modules generate the IRQ$0,$ IRQ$10$ and IRQ$31$ interrupt requests, and what are their CMSIS typedef enumeration labels? Examine the Interrupt Vector Assignments table in the KL$25$Z subfamily reference manual and the MKL$25$Z$4.$h file $($or appropriate device.h file for a different MCU device$).$

The next several questions involve configuring registers so that if interrupts IRQ$0,$ IRQ$10$ and IRQ$31$ are requested simultaneously, the CPU responds as requested. For each question, explain what values must be loaded into which registers, and then write C code which uses the CMSIS functions to perform that operation.

Interrupts are serviced in order IRQ$10,$ IRQ$0,$ IRQ$31.$

Interrupts are serviced in order IRQ$0,$ IRQ$31,$ IRQ$10.$

No interrupts are serviced.

We wish to enable IRQ$13$ but disable IRQ$24.$ What value needs to be loaded into which register bits, and what is the CMSIS code call to accomplish the same?

We wish to determine if IRQ$7$ has been requested. Which register and which bit will indicate this? What is the CMSIS call which will reveal the information?

Which register can an exception handler use to determine if it is servicing exception number $021?$ What value will the register have? What is the CMSIS interface code to read the IPSR?