Expand the registerfile from PROJECT lA by adding a B-Data Bus and a Functional Unit to the 32 registers in order to obtain 32-bit version of the Datapath shown in Figure 1 on page 3. Figure 1 is taken from Figure 7-19 in Mano and Kime. You should write a gate-level VHDL models for the Functional Unit. The architecture should use a 32-bit ripple adder. The Functional Unit should have the functionality defined on the Table 1 on page 2. Set all gate propagation delays to 5 ns and simulate arithmetic operations.