f$.$ With input of $Q1=$logic$1($VoD$),$ record the result for each:

$(3)$ If input to Q$2($DG$1)=$ logic $0,$ output $($PR$1)=q,$

$(4)$ If input to Q$2($DG$1)=$ logic $1,$ output $($PR$1)=q,$

$(5)$ Based on the results, what type of logic gate does this circuit represent?

$($a$)$ AND

$($b$)OR$

$($c$)$ NAND

$($d$)$ NOR

Part $2$

g$.$ Place the components and wire up the circuit shown in Figure $2($left$).$ Use the same settings as before.

rigure $$: Log$$c circuit with parallel NMOS.

Left: Input of Q$2$ set to logic $0(0$ V $).$ Right: Input of Q$2$ set to logic $1($Voo$).$

h$.$ Set the simulation mode to "Interactive". Simulate the circuit.

i$.$ With input of $Q_2=$logic$0($GND$),$ record the result for each:

$(6)$ If input to Q$1($DG$1)=$ logic $0,$ output $($PR$1)=q,$

$(7)$ If input to Q$1($DG$1)=$ logic $1,$ output $($PR$1)=q,$

j$.$ Now change the input of transistor $Q2$ to $V_{DD}=5V,$ as shown in Figure $1($right$).$

k$.$ With input of $Q_2=$logic$1(V_{DD}),$ record the result for each:

$(8)$ If input to Q$1($DG$1)=0,$ output $($PR$1)=q,$

$(9)$ If input to Q$1($DG$1)=1,$ output $($PR$1)=q,$

$(10)$ Based on the results, what type of logic gate does this circuit represent?

$($a$)$ AND

$($b$)OR$

$($c$)$ NAND

$($d$)$ NOR

THIS IS PAGE $2$ TO A PREVIOUS POST, I COULDNT FIGURE OUT HOW TO SEND THEM TOGETHER