Find the logic for the below description use a minimum number of flip flops. In this part of the lab, we will refer to the D input of the dif primitive as DIN. You will need to create logic that computes DIN as a function of Q and the D, EN, and RSIN inputs. Remember that RSTN is a synchronous reset, which means that we cannot connect it to the asynchronous clear input of the dff primitive. Instead, we have to use it, along with inputs D and EN, to compute DIN. You will need to create this logic, based on the below requirements: a. If RSTN is 0, then the next state of the flip-flop should be 0, regardless of the value of D or EN. b. If RSTN is 1 and EN is 1, then DIN should be equal to D c. If RSTN is 1 and EN is 0, then the flip-flop value should not change at the clock edge. Note that not all of these requirements are stated explicitly in terms of the value that DIN should be. You must determine what DIN should be in order to match the required behavior for each of these cases