Question: For a computer architecture with multi-level paging, a page size of 4KB and 64-bit physical and virtual addresses: a. What is the smallest possible size

For a computer architecture with multi-level paging, a page size of

For a computer architecture with multi-level paging, a page size of 4KB and 64-bit physical and virtual addresses: a. What is the smallest possible size for a page table entry, rounded up to a power of 2? b. Using your results above, and assuming a requirement that each page table fits into a single page, how many levels of page tables would be required to completely map the 64-bit virtual address space? The following figures show the Solaris Virtual Memory Layout on different hardware platforms

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