For a direct$-$mapped cache design with a $32-$bit byte address, the following bits of the address are

used to access the cache.

Tag Index Offset

$31$:$1110$:$54$:$0$

$1.$ What is the cache block size $($in words$)?$

$2.$ How many entries $($blocks$)$ does the cache have?

$3.$ How many bits are used for Tag?

$4.$ What is the ratio between total bits required for such a cache implementation over the

data storage bits