For a direct$-$mapped cache with a $32-$bit address, the following bits of the address are used to access the cache. Tag Index Offset $31-109-54-0$ a$)$ What is the cache block size $($in words$)?$ b$)$ How many entries does the cache have? c$)$ What is the ratio between total bits required for such a cache implementation over the data storage bits? Beginning from power on$,$ the following byte$-$addressed cache references are recorded Address Hex $00041084$ E$8$ A$04001$E $8$C C$1$C B$4884$ Dec $041613223216010243014031001802180$ d$)$ For each reference, list $(1)$ its tag, index, and offset, $(2)$ whether it is a hit or a miss, and $(3)$ which bytes were replaced $($if any$).$