For each cache configuration below, fill in the corresponding rows to show whether each access is a hit or a miss. Also indicate the set that would be checked given the memory address. The block size for all caches is one word (4 bytes). 8 word direct mapped cache 2-way set associative cache with 8 word capacity 4-way set associative cache with 8 word capacity Input rules: Set is an integer Hit is 1 if the access was a hit, or o otherwise Direct Set: Two-way Set: Four-way Set: Hit: Hit: Hit: References: 0x8e378878 integer integer integer Oxab489dd8 integer integer integer Ox8aa5461c integer integer integer Oxa081ecb8 integer integer integer Oxaba2ddf8 integer integer integer 0x8e378878 integer integer integer 0x8e378878 integer integer integer Oxa6a2ddf8 integer integer integer oxca95bf1c integer integer integer 0x8aa54610 integer integer integer Oxa081ecb8 integer integer integer What are the miss ratios for each of the three caches given the above memory accesses? How many cache evictions occured in each? (A cache eviction is when something in the cache is removed.) Write your answers in the table below. Input rules: Miss rate is a decimal value between 0 and 1. It can be entered as a fraction. Evictions is an integer Miss rate Evictions Cache Direct integer Two-way integer Four-way integer