For problems in this practice set, it may be helpful to refer to the following diagram of the single$-$cycle processor and control.

Consider the following instruction:

AND Rd$,$ Rs$,$ Rt

Interpretation: Reg$[$Rd$]=$ Reg$[$Rs$]$ AND Reg$[$Rt$]$

What are the values of the control signals generated by this control function?

RegDst $=1$

ALUOp $=0$b$0010$

Branch $=0$

MemWrite $=0$

MemRead $=0$

ALUSrc $=0$

MemtoReg $=0$

RegWrite $=1$

Which resources$/$blocks perform useful function for this instruction?

Which resources$/$blocks produce outputs, but their outputs are not used for this instruction? Which produce no outputs?