For problems in this practice set, it may be helpful to refer to the following diagram of the single-cycle processor and control. The basic single-cycle MIPS implementation in the provided figure can only implement some instructions. New instructions can be added to an existing instruction set architecture (ISA), but the decision whether or not to do that depends, among other things, on the const and complexity the proposed addition introduces into the processor datapath and control. For this problem, refer to the following proposed new instruction: LWI Rt, Rd (Rs) Interpretation: Reg[Rt]=Mem[Reg[Rd]+Reg[Rs]]