For the Code below Answer the Following Questions:

The module below is carry$-$select adder of unsigned numbers,

The Algorithm has $3$ inputs and $2$ outputs:

Input $A$ first addition operand

Input $B$ second addition operand

Input Cin $$ carry in input

Output result $$ addition output

Output Cout $$ carry outputQ$1$: Attached is the code of $16-$bit carry select adder Verilog code, you need to pipeline this design

Q$2$: Write a testbench with verification code to test your implementation and submit it to blackboard

Your testbench should have $4$ different testcases, each cycle a new input should be given