For the following MIPS instruction sequence, complete the pipeline cycle diagram for the standard 5- stage pipeline without forwarding. Assume register file writes occur in the first half cycle and reads in the second half cycle.

i1: lw r1, 0( r5 ) // reg[1] memory[ reg[5] + 0 ]

i2: add r3, r1, r2 // reg[3] reg[1] + reg[2]

i3: addi r4, r3, 1 // reg[4] reg[3] + 1

i1:lw IF ID EX MEM WB

i2:add IF

i3:addi