For the question below, you will simulate a 64-byte cache with different configurations. In each case the following list of memory addresses are accessed: 16, 32, 4, 65, 16, 80, 76, 224, 20, 16, 36, 172, 20, 36, 24, 65 These addresses are decimal byte addresses For each problem, start with an empty cache and do the following: 1) list each memory access and label as a hit or miss and 2) show the final contents of the cache. Use a 2-way set associative 64 byte cache with one-word blocks. Assume LRU replacement