For the questions in this section, consider an architecture with $32-$bit words, and L$1$ data cache with $128$ bytes of capacity, direct mapping, and write$-$back, write$-$allocate writing.

a$)$ If the cache has blocks of $1$ word$($s$)(4$ bytes$),$ how many bits should the Tag field have?

b$)$ If the cache has blocks of $2$ word$($s$)(8$ bytes$),$ how many bits should the Index field have?

c$)$ If the cache has blocks of $1$ word$($s$)(4$ bytes$),$ how many bits should the Offset field have?

Consider configuring the cache with blocks of $432-$bit words $(16-$byte block$).$ Assume that, initially, the word in memory position x has a value of $10$x$.$ Consider that the following sequence of memory accesses was performed:

$1.$ Load Word $(4)$

$2.$ Load Word $(8)$

$3.$ Store Word $(20),$ Value $1234$

$4.$ Load Word $(24)$

$5.$ Load Word $(128)$

d$)$ After the sequence of accesses, what is the value $($in decimal$)$ stored in the Tag field in line zero of the cache?

e$)$ After the sequence of accesses, what is the value $($in decimal$)$ of the word stored at offset eight in cache line zero?