For the single cycle processor design shown in Figure $1,$ what is the minimum clock cycle time of this design?

Assume the component delays are as below, and the hold$-$time for register and memory is relatively small and

can be ignored.

register setup time: $0\mathrm{.}5ns$

register $($clock$-$to$-$Q$)$: $0\mathrm{.}5$ns

Instruction$/$Data memory access $($for either read or write$)$: $5\mathrm{.}0$ns

main control: $0\mathrm{.}8ns$

ALU local control: $0\mathrm{.}5$ ns

register file: $1\mathrm{.}0ns$

MUX:$0\mathrm{.}5$ns

extender: $0\mathrm{.}1ns$

ALU:$2\mathrm{.}0$ns

adder: $0\mathrm{.}5ns$